1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and relates to a reset cancel operation at the time of a return from power shutdown.
2. Description of the Related Art
In recent years, the trend of energy saving in consideration of environmental issues has been leading to a growing demand for a reduction in power consumption to semiconductor integrated circuits. For example, to reduce power consumption, there is a method of shutting down power to a part of subsystems in a semiconductor integrated circuit.
At the time of returning power to a subsystem for which power has been shut down, initialization is required after power is supplied, and the initialization is performed before starting a normal operation. During the initialization, the state of the subsystem is initialized by actively causing a signal change to a storage element such as a flip-flop within the subsystem. Therefore, during the initialization, high power consumption is often required due to poor execution of clock gating. For solving this problem, Japanese Patent Application Laid-Open No. 2002-312073 discusses a technique for reducing power consumption by dividing a frequency of a clock input during initialization to reduce a performance.
In recent semiconductor devices, the number of regions for which power is shut down (this region is generally referred to as a “power control target” or a “power domain”, and will hereinafter be referred to as a “power domain”) is increasing. Arranging a plurality of subsystems for realizing functions in different power domains allows power to be shut down to a power domain where a subsystem for realizing an unnecessary function is arranged, thereby enabling a reduction in power consumption.
Each power domain requires an initialization operation (especially, a start of clock supply for placing a flip-flop into an initial state and cancel of a reset signal) after a restart of power supply. Further, commonly-used semiconductor integrated circuits synchronize initialization (the timing of issuing a clock and a reset signal and the timing of cancelling the signals) to reduce a possibility of error occurrence, when resetting a plurality of internal subsystems. However, an overlap of clock supply operations for initialization for the plurality of power domains results in concentration of and an increase in instantaneous power consumption during the initialization. The technique discussed in Japanese Patent Application Laid-Open No. 2002-312073 can reduce a peak of power consumption to some degrees, but cannot solve concentration of an increase in instantaneous power consumption.